1. Field of the Invention
The invention relates to computers having system management mode operations, particularly where the memory for the system management mode is located in the main memory space of the computer and accessible by conventional applications and thus must be write protected.
2. Description of the Related Art
Microprocessor-based computer systems have been increasing in performance at a tremendous rate. Much of this increase has been based on the improvements in the microprocessor itself. For example, clock speeds are reaching those previously used only by mainframe computers. However, affordable memory device performance has not been increasing at the same rate. Indeed, dynamic random access memory (DRAM) performance has flattened out recently, with the majority of the effort being concentrated on increasing device storage size. Thus main memory has become a bottleneck.
Cache memory systems, where a small amount of very fast, expensive static RAM is used to store copies of the data, have made the problem somewhat less severe, but the designs are very complicated and expensive. Further, the poor memory performance returns when access must be made to main memory. So there still is a need to improve the performance of the main memory system.
Page mode memory devices provide one way to increase memory system performance. If consecutive accesses are made to the same row address, referred to as the same page, only column addresses need be provided. This allows a dramatic reduction in cycle time for those cases, referred to as page hits. This is a quick gain and relatively easily made by itself, but more performance is always desired.
In many processors, the address is provided before the data portion of the cycle. This is referred to as pipelining and allows a performance increase in the memory systems. All of the address decoding can be started before the data portion begins, so that partially parallel operations can occur.
In most cases this overlap is somewhat minimal, one or two clock cycles, as the related systems cannot handle much more complexity. For example, the memory controller is conventionally built as a synchronous controller, based on a major state machine to control events and advancing on the processor clock edge. As the complexities of the microprocessor and the computer system increase, the conventional memory controller design becomes very limiting. It is exceedingly difficult to build a major state machine to handle all the possible cases. The complexity is daunting, if not overwhelming. As a result, numerous potential performance improvements have to be limited. Usually this means that any pipelining is limited and there are very few parallel operations. While some designs allowed write operations to be posted, this just further increased complexity in other ways. As a result, some other feature was sacrificed, so potential gains were lost.
Memory system performance is also a trade off between cost and speed. While conventionally 80 ns DRAMs have been used, 60 ns devices are available, though at a slightly higher cost. While prior memory controllers could utilize differing speeds of DRAMs, allowing the user to make the speed versus cost tradeoff, a mixed speed system did not obtain any benefits. The memory controller could use different speed DRAMs, but only one actual speed of operation was allowed in the system. The memory controller thus ran at the speed of the slowest of the installed DRAMs. This did not allow the user to have fast memory areas, such as the base memory area, and slow memory areas, such as extended memory locations in the main system memory controlled by the memory controller. This limitation arose again because of the complexities of memory controllers.
Thus there are memory system performance gains that could be achieved, but conventional design limitations render them only potential, not practical. Therefore it is clearly desirable to have a memory controller which makes maximum use of processor address pipelining, can run numerous cycles concurrently in the greatest number of cases and can effectively use different speed memory devices.
Additionally, certain microprocessors, such as the 80386SL and the 80486SL from Intel Corporation have included a mode referred to as system management mode, which is entered upon receipt of an SMI or system management interrupt. Recently the P5 or Pentium processor from Intel has added this feature. The P5 is a very high performance microprocessor having a superscalar architecture and integrated and separate code and data caches. The data bus is 64 bits wide and 8 parity bits are provided. The data cache is a write-back design having a 32 byte line width.
An SMI pin is used to enter SM mode and a signal referred to as SMIACT* is provided by the P5 or Pentium to indicate operation in SM mode. When an SMI is asserted, an Intel microprocessor maps a portion of memory referred to as the system management memory (SMRAM) into the main memory space. The entire CPU state is then saved in the SMRAM in stack-like, last in/first out fashion. After the CPU state is saved, the microprocessor begins executing an SMI handler routine, which is an interrupt service routine to perform specific system management tasks, like reducing power to specific devices. While the routine is executed, other interrupt requests are not serviced, and are ignored until the interrupt routine is completed or the microprocessor is reset. When the SMI handler completes its task, the CPU state is retrieved from the SMRAM, and the main program continues.
In the first processors to use SMIs, the Intel Corporation 80386SL and 80486SL microprocessors, the SMRAM is mapped into the main memory space between 30000h and 3FFFFh. Data regarding the CPU state is stored starting at 3FFFFh going down like a conventional stack. After the CPU state is saved in the SMRAM, the microprocessor starts the SMI handler at memory address 38000h located in the SMRAM space. In the 80386 and 80486 microprocessor generations, the SMI start address is stored in a non-accessible register so that it cannot be changed by the programmer. Similarly, the use of the memory space between 30000h and 3FFFFh is preset into the microprocessor and unchangeable. Although this placement of the SMRAM and starting address is stable and known, it is often inconvenient. Any data stored in the main memory space between 30000h and 3FFFFh before the SMI is asserted is likely to be overwritten by the SMI handler and lost, unless hardware is developed which maps in special memory and maps out conventional memory. This mapping requirement has the problem of requiring extra logic and forces abrupt changes in memory contents necessitating flushing of any cache memory system. This has a cost and performance drawback. If the mapping is not performed, the software must be carefully designed around the memory space used by the SMRAM in order to prevent inadvertent loss of data.
To remedy this inconvenience, the Pentium or P5 microprocessor permits the SMI handler starting address and the location of the SMRAM space to be changed by the user. Under the Pentium design, the SMI starting address stored in the microprocessor register is initially set to the conventional 30000h value. Consequently, when the first SMI is asserted, the SMI handler starts at address 38000h. While the SMI handler routine is executing, however, it may provide a different area of memory to be used as the SMRAM. This new SMRAM may start at any location in the main memory space chosen by the programmer. The SMRAM comprises a 64 kbyte block beginning at the new SMRAM start address. When the SMI handler finishes, the new starting address replaces the old starting address in the microprocessor's SMI starting address register.
When the next SMI is asserted, the microprocessor maps the new 64 kbyte block of memory into the main memory space as the SMRAM, and starts the SMI handler at the new starting address at the midpoint of the new SMRAM. For example, during the first SMI service routine, the programmer may change the SMRAM starting point from 030000h to 100000h. When the SMI is next asserted, the microprocessor maps the SMRAM into main memory space between 100000h and 10FFFFh. The microprocessor then references address 108000h for the SMI handler. This feature thus allows the programmer to choose a more convenient location in the main memory for the SMRAM.
Although the ability to relocate the SMRAM provides a convenient option to the programmer, it presents a problem. Because of the very high level of code placed in the SMRAM and its sensitive nature, it is very desireable to write protect this area of memory when it is located in the main memory space to prevent inadvertant overwriting of the code. Many problems could result if the system management code was overwritten, as the system would not respond properly to an SMI. When the SMRAM was located external to the main memory space, this was not a problem as the mapping of the memory to an area outside of the normal main memory space prevented inadvertant writes to the area and so write protection was not necessary. So when the SMRAM area is in the main memory space it must be write protected.
But write protecting this block adds a further problem. Conventionally write protection is done based on physical addresses. Thus once write protected, the area would stay write protected until specific instructions are performed. The processor could not store the internal state values upon entry into the system management mode as those instructions would not be performed prior to the automatic state storage operations. This would prevent a proper restoration of the machine state. Further, the system management code would not be able to use a reserved area in the SMRAM for its own data storage until after the special instructions are performed. The area would be write protected and thus could not be used for scratchpad or more permanent storage. Using memory elsewhere might not be possible as that would possibly interfere with applications code present at those locations. This write protect bit could also prevent write operations to certain locations once system management mode was entered.
Therefore it is desireable to resolve this write protection problem with SMRAM so that the SMRAM can safely be placed in main memory and yet operate properly during system management mode operations.